The manufacture of integrated circuits (ICs) typically includes the formation of metallization layers which are patterned to provide interconnection between devices. Some IC interconnections are programable, either with fuses or anti-fuses. Unprogrammed fuses provide a low resistance link between or within metallization layers which can be programmed by being blown. That is, the fuse can be caused to be non-conductive by applying a sufficiently high current across it to blow.
Anti-fuses operate in the opposite fashion, i.e., the unprogrammed structure used to form the anti-fuse has an intrinsically high resistance, and the programmed structure has a relatively low resistance. By applying a programmable current, the electrical resistance through the anti-fuse material is greatly reduced providing a conductive link between or within metallization levels. Typical prior art anti-fuse materials include: amorphous silicon, amorphous carbon, carbon, germanium, selenium, compound semiconductors such as GaAs, SiC, AlP, InSb and CdTe, and ceramics such as Al2O3.
One prior art anti-fuse structure is shown in FIG. 1. Specifically, the structure shown in FIG. 1 comprises a substrate 12 such as a Si wafer. An oxide layer 14 overlays the substrate, and can be formed by a variety of well known deposition processes such as chemical vapor deposition. A metal layer 16 is then formed on the oxide layer utilizing conventional deposition processes such as evaporation or sputtering. A second oxide layer 18 is formed over the metal layer and a via 20 is formed in the second oxide layer utilizing conventional lithography and reactive-ion etching (RIE). One of the above mentioned anti-fuse materials is then formed in the via to form an anti-fuse structure 22. A second metal layer 24 is then formed over the structure.
Programming of the anti-fuse structure of FIG. 1 can be accomplished by providing a voltage of 4-10 volts between the metal layers. Before programming, the anti-fuse structure typically has a resistance of above 1 giga-ohm for a 1 μm diameter via. A programmed anti-fuse forms a conductive path 26 between the metal layers having a resistance of about 20-100 ohms.
Anti-fuse structures allow for much higher programable interconnection densities than standard fuse structures as well as smaller current and power for the non-programmed elements. A major problem with prior art anti-fuse structures is that dedicated lithographic masking levels are required to fabricate the same. Not only does the use of such dedicated lithographic masking levels add additional cost to the overall process, but it adds to the complexity of the same.
In view of the above mentioned problems with prior art anti-fuse structures, there is a continued need to develop a new and improved method in which an anti-fuse structure is fabricated without employing dedicated lithographic masking levels.
Co-assigned U.S. application Ser. No. 09/469,374, filed Dec. 22, 1999, describes one method of forming an interconnect structure wherein dedicated masking levels are not employed. In the '374 application, an interlevel dielectric (ILD) layer is formed on top of a substrate having a first level of electrically conductive features formed therein and then vias, at least one via being a slot via, are formed in the ILD layer to expose portions of the first level of electrically conductive features. Next, a conformal anti-fuse material is formed on the ILD and the anti-fuse material is patterned to form spaces in which a second level of electrically conductive features is formed. Etching is conducted to remove anti-fuse material from the spaces and the vacant spaces are then filled with a conductive material.
Alternative methods to the one disclosed in the '374 application are continuously being sought in which fewer processing steps are employed. The present invention describes an alternative method to the method disclosed in the '374 application and it represents an improvement there of since the anti-fuse material is formed on the surface of the substrate prior to ILD deposition. This eliminates extra processing steps required in the '374 application to create a standard contact; therefore the impact and/or influence on the contact itself is greatly minimized.